Detailed Document on the UltraSPARC T2 (Niagara 2)

A side-effect of open-sourcing its SPARC designs and selling chips and service to OEMS is that a lot of information is being made available by Sun. For example, "UltraSPARC T2 Supplement to the UltraSPARC Architecture 2007" is a 1100 page detailed description of UltraSPARC T2.

Here's the table of contents:

1. UltraSPARC T2 Basics.
2. Data Formats.
3. Registers
4. Instruction Format
5. Instruction Definitions
6. Traps
7. Interrupt Handling
8. Memory Models
9. Address Spaces and ASIs
10. Performance Instrumentation
    
11. Implementation Dependencies
    
12. Memory Management Unit
13. Clocks, Reset, RED_state, and Initialization
14. CMT
15. Noncacheable Unit (NCU) and Boot ROM Interfaces
16. Error Handling
17. Memory Controller
18. Power Management
19. Configuration and Diagnostics Support
20. Hardware Debug Support
21. Stream Processing Unit and Random Number Generator
22. PCI Express Interface Unit (PIU)
23. Network Interface Unit: Introduction
24. Network Interface Unit: Interrupts and Virtualization
25. Network Interface Unit: Receive Packet Classification
26. Network Interface Unit: Receive DMA
27. Network Interface Unit: Transmit DMA Channels
28. Network Interface Unit: Ethernet Media Adaptation Controller (MAC)
29. Network Interface Unit: Ethernet SerDes

I like that Sun has included a hardware-based random number generator in the chip.